1. Field of the Invention
This invention relates to a process for forming a crystalline semiconductor film and more particularly to a process for forming semiconductor film with large grain sizes and controlled grain boundary position, capable of forming semiconductor devices such as a thin film transistor (TFT) of high performance.
2. Related Background Art
Heretofore, a process for solid phase growth of a crystalline film by annealing an amorphous thin film formed in advance on a substrate at a lower temperature than the melting point has been proposed as one of processes in the field of crystal formation technology to make a crystalline film grow on a substrate such as an amorphous substrate. For example, a process for formation of crystal by annealing an amorphous Si film having thickness of about 100 nm formed on the surface of amorphous SiO.sub.2 in a N.sub.2 atmosphere at 600.degree. C., thereby crystallizing the amorphous Si thin film to obtain a polycrystalline film having grain sizes of about 5 pm is reported [T. Noguchi, H. Hayashi and H. Ohshima, 1987, Mat. Res. Soc. Symp. Proc., 106, Polysilicon and Interfaces, 293, (Elsevier Science Publishing, New York 1988)]. Since the surface of the polycrystalline film obtained by the process remains flat, it is possible to form electronic devices such as MOS transistors or diodes thereon. Furthermore, the average grain sizes of the polycrystalline film are larger than those of ordinary polycrystalline film obtained by LPCVD process, thus the devices formed with the polycrystalline film have a relatively high performance.
However, the polycrystalline film obtained by the above-mentioned process for formation of crystal has relatively large crystal grain sizes, but the distribution of grain sizes and the position of crystal grain boundary are not controlled, because the crystallization of amorphous Si film is based on solid phase growth of crystal nuclei generated at random in the amorphous Si film by the annealing in that case. That is, generation of crystal nuclei at random leads to random positioning of grain boundary, resulting in distribution of grain sizes in a broad range. In spite of merely large average crystal grain size, the above-mentioned process still has the following problems.
For example, in the case of MOS transistors, generally the gate size is as large as or less than the average crystal grain size and thus the gate region has a part containing no grain boundary and a part containing a few crystal grains. Electrical characteristics naturally change between the part containing no grain boundary and the part containing a few crystal grains. Thus, a large fluctuation develops in the characteristics between a plurality of devices, and when an integrated circuit or the like is to be formed, the fluctuation in the crystal grain size has been a considerable bar to the improvement of integrated circuit performance.
As to the fluctuation in the grain size among the problems encountered in the polycrystalline film of large grain size by the solid phase crystallization, a process for controlling it is proposed in Japanese Patent Application Kokai (Laid-Open) No. 58-56406, as will be explained below, referring is FIG. 9. As shown in FIG. 9A, an amorphous Si film 42 is formed on a substrate 41 of Si single crystal having a heat oxidation film on the surface. Then, thin film pieces 44 of a different material from that of the amorphous Si film 42, for example, SiO.sub.2, are periodically provided on the amorphous Si film. Then, the entire substrate is annealed in an ordinary heating furnace, whereby crystal nuclei 43 are preferentially formed at positions of amorphous Si film 42 in contact with the peripheral parts of thin film pieces 44. By making the crystal nuclei further grow, the amorphous Si film 42 is crystallized throughout the entire area, and a polycrystalline film composed of a group of crystal grains 45 with larger grain size, as shown in FIG. 9B can be obtained.
However, it is the current situation that the positions of crystal grain boundaries are not satisfactorily controlled even by the above-mentioned process, because in the above-mentioned process preferential formation of nuclei takes place at the peripheral parts of the thin film pieces 44 due to local effect of elastic energy at positions of amorphous Si film 42 in contact with the peripheral parts of the film pieces 44. Consequently, a plurality of nuclei generate along the peripheral parts, but it is difficult to control the number of nuclei.
Furthermore, in order to obtain a polycrystalline film in the above-mentioned process, annealing is carried out after the thin film pieces 44 of a different material from that of amorphous Si film 42 are brought into contact with the amorphous Si film 42, and this procedure sometimes leads to contamination of polycrystalline film with the constituent element of thin film pieces 44 as an impurity, which is a problem in the production of a polycrystalline film of high quality.
Control of positions for formation of nuclei in the solid phase growth of amorphous Si film is also proposed in Japanese Patent Application Kokai (Laid-Open) No. 63-253616, as will be explained below, referring to FIG. 10. N.sup.+ ions 53 are locally implanted in an amorphous Si thin film 52 on an insulating substrate 51 to form ion-implanted regions 54. Then, crystal nuclei are preferentially generated in other region than the ion-implanted regions 54, that is, region 52, by annealing.
However, in the above-mentioned process, the annealing is carried out after a different material from the amorphous Si, that is N.sup.+ ions, has been implanted, and thus N atoms sometimes remain in the crystalline Si as an impurity. In that case, N atoms act as an electrically active impurity and sometimes inhibit formation of devices of high performance.